Objective

The main objective of the Simulation and Modeling to Enhance Performance of Multicore Processor Systems project is to propose code and/or operating system (scheduling) modifications to improve performance of Army applications executed on emerging technologies. To achieve such goal the project has being divided in two parts.

Part 1: NMSU/LANL Monte Carlo Processor-Performance Model

Model Development Goal

• Fast Performance Prediction
• Fast Design Space Exploration
  • What if the double-precision FP unit is fully pipelined?
  • Should we improve the branch unit?
• Fast Bottleneck Analysis
  • Which processor component hurts performance the most?



Modeling Tools


• IBM Cell, Sun Niagara, and Intel Itanium Monte Carlo models (in-order processors)
  • Accurately predicts performance (to within 10%) on suite of scientific applications
• Tools for parameter collection on AMD Opteron platform

 

Part 2:  Performance of Simultaneous Multithreaded (SMT) Processor

Goal:
Improve Simultaneous Multithreaded (SMT) processor throughput using hardware thread priorities and SMT mode.



Simultaneous Multithreading (SMT)
Two or more threads simultaneously execute independent instruction streams, potentially doubling throughput



Problems due to Interference Sharable resources:
Microarchitecture/Pipeline Memory (competing working sets)
TLB (virtual-to-real address translation)

Sharing characteristics:
Interference depends on characteristics of applications sharing at cycle-level granularity

Performance effects:
Reduced SMT throughput In extreme cases, throughput less than processor without SMT (Single-Threaded)